1. Field of the Invention
The invention relates to forming a complementary metal oxide semiconductor, more particularly to the production of a gate contact in the complementary metal oxide semiconductor.
2. Description of the Prior Art
Generally, gate contact metal oxide semiconductor (GCMOS) will have gate contact (GC) implantation by the zero degree angle into source site only. In the fabrication process, when the polysilicon layer becomes narrower, the implant will be very aligned. Therefore, the operation for the overlay rule of GC implanting to the source region of the active area will become the major issue of the above fabrication process.
In the conventional method, and referring to FIG. 1A, firstly a semiconductor substrate 10 with an oxide layer 11 upon the semiconductor substrate 10 is provided. Again, as in FIG. 1A, defining polysilicon 12 as gate 12 is carried out.
Sequentially, as FIG. 1B, photoresist mask 13 is formed on top surface of oxide layer 11 and it can cover half of gate 12. Gate contact implanting is achieved as a poor overlay region 14, about 0.09 .mu.m.
Then, as shown in FIG. 1C, source/drain is implanted as regions 15A and 15B. Then, annealing can be completed soon by using rapid thermal processing (RTP) at 1000.degree. C.
Then, as shown in FIG. 1D, silicon nitride 16 is deposited and etched as spacer 16 upon top surface of oxide layer 11.
Finally, as shown in FIG. 1E, salicide can be formed as salicilide zone 17 on top surface of gate 12 and top surface of oxide layer 11 by using rapid heating processing.
Normally, the development of quarter-micrometer CMOS devices requires so-called substrate engineering as well as drain engineering. The formation of the bulk doping profile is one of the most important technologies in the quarter-micrometer range.
However, obviously, the constructed structure of the semiconductor device by the above progress does not satisfy the requirement of the next generation. Therefore, it is necessary to develop another fabrication process in the field of the smaller size in the semiconductor industry, such as 0.18 .mu.m.